library verilog;
use verilog.vl_types.all;
entity display is
    port(
        dig_out_021     : out    vl_logic_vector(5 downto 0);
        scan_clk_021    : in     vl_logic;
        seg_out_021     : out    vl_logic_vector(6 downto 0);
        data0x_021      : in     vl_logic_vector(3 downto 0);
        data1x_021      : in     vl_logic_vector(3 downto 0);
        data2x_021      : in     vl_logic_vector(3 downto 0);
        data3x_021      : in     vl_logic_vector(3 downto 0);
        data4x_021      : in     vl_logic_vector(3 downto 0);
        data5x_021      : in     vl_logic_vector(3 downto 0)
    );
end display;
